1. Field of the Application
The subject application relates to test and debug of semiconductor chips and, more specifically, for orientation/alignment of a chip image to enable test and debug, such as, e.g., testing using device photoemission.
2. Related Art
It has been well known in the art that semiconductor devices emit light upon change of states, e.g. transistors switching on/off. This phenomenon has been used successively to test and debug semiconductor circuits using, e.g., infrared emission microscopy (IREM) and time-resolved emission microscopy. It has also been known in the art to use lasers to test and debug semiconductor circuits by examining modulations in the reflected laser light. The technique is generally referred to as LP (laser probing). Also, with the shrinking of the size of new devices, the devices are made “leaky” so that electron-hole recombination occurs during the static off state of the device, leading to IR emission. This emission increases as design rule decreases. That is, this phenomenon will express itself more pronouncedly as device generation progresses. This static emission can also be used for debug and test of semiconductor circuits.
As can be understood, beneficial use of the emission detection techniques can only be made if the location of the emission can be isolated and accurately linked to the devices that emit the light. Similar issue applies to laser-based systems, i.e., to use such tester one must resolve which device caused the modulation in the reflected laser light. However, as design rule shrinks, the density of the devices increases, making it very difficult and sometimes impossible to isolate the device that emits the light or modulates the laser beam. Additionally, emissions from neighboring devices enter the optical path of the testing system, thereby further complicating the task of isolating the emitting or modulating device. Incidentally, while design rule shrinking leads to improved static emission, it also makes it more difficult to isolate the emitting devices.
Alignment of the CAD design to the chip features is increasingly becoming very difficult as the chip geometries have shrunk below the optical resolution limit. Conventionally the user selects three or more points on the chip CAD design and makes a rough guesses where the same points lie on the blurry chip image, which is acquired by illuminating the chip. The procedure computes the six value Translation Matrix which allows one to map from the CAD space to the chip space to account for X, Y, Theta mis-registration and to correct for mechanical distortion caused on the chip by mechanical and thermal stresses. However the accuracy of this method is now limited by the optical resolution limit. These issues are discussed in U.S. Pat. No. 7,636,155 which discloses method capable of extreme sub-optical resolution of photon emitting transistor if the CAD and the chip are aligned perfectly. But it needs extremely accurate alignment of CAD geometry to the actual transistor on a chip. To resolve photo emissions with double the optical resolution requires a registration accuracy of one fourth the optical resolution limits.
In the above mentioned patent the photoemission could be accurately aligned by aligning the centroid of the photoemission of an isolated transistor to the centre of the CAD geometry of the transistor. However in practice isolated photoemission sites are not always available. For the newer small geometry transistors, the photoemission from different transistors begins to overlap. For multiple overlapping emissions, the centroid of the photoemission will lie somewhere inside the polygon defined by the centre of the emitting transistors. The accuracy of the alignment by this approach becomes unacceptable.
In order to enable progress in the semiconductor industry pursuant to “Moore's Law,” designers will continue to decrease design rules and increase device density. Therefore, the need for debug and testing becomes increasingly indispensable and the difficulty of resolving emitting/modulating devices must be solved. Accordingly, there is a need in the art to provide improved resolution of devices on the tested chip, thereby requiring an improved approach to alignment of the chip image.
Another problem in the art is that each emitting transistor is a point-source omni-radiator, meaning it emits light in all directions. Consequently, on various situations it happens that the light is radiated in a direction towards the interconnects, is then reflected by a metal line, and is then propagated through the silicon layer and is collected by the objective lens. Under such circumstances it is difficult to determine where the emission has originated from in order to resolve the emitting devices. Therefore, an improvement is needed to enable resolving the emitting devices even in devices where metal line reflect the emission.